The serial port is used to connect basically _____ and processor
1.I/O devices
2.Speakers
3.Printer
4. Monitor
A complete transfer operation over the BUS, involving the address and a burst of data is called _____
1.Transaction
2.Transfer
3.Move
4.Procedure
IDE disk is connected to the PCI BUS using ______ interface.
1.ISA
2. ISO
3.ANSI
4.ANSI
In a 32 bit processor, the A0 bit of the address line is connected to _____ of the parallel port interface.
1.Valid bit
2.Idle bit
3.Interrupt enable bit
4.Status or data register
In a serial port interface, the INTR line is connected to _____
1.Status register
2.Shift register
3. Chip select
4.None of the mentioned
In the output interface of the parallel port, along with the valid signal ______ is also sent.
1. Data
2.Idle signal
3.Interrupt
4.Acknowledge signal
The disadvantage of using a parallel mode of communication is ______
1.It is costly
2.Leads to erroneous data transfer
3. Security of data
4.All of the mentioned
The double buffer is used for _________
1.Enabling retrieval of multiple bits of input
2.Combining the input and output operations
3.Extending the buffer capacity
4.None of the mentioned
The key feature of the PCI BUS is _________
1.Low cost connectivity
2. Plug and Play capability
3.Expansion of Bandwidth
4.None of the mentioned
The key feature of UART is _________
1. Its architectural design
2.Its simple implementation
3.Its general purpose usage
4. Its enhancement of connecting low speed devices
The mode of transmission of data, where one bit is sent for each clock cycle is ______
1.Asynchronous
2.Parallel
3. Serial
4.Isochronous
The standard used in serial ports to facilitate communication is _____
1. RS-246
2.RS-LNK
3. RS-232-C
4. Both RS-246 and RS-LNK
The Status flag circuit is implemented using _____
1.RS flip flop
2.D flip flop
3. JK flip flop
4.Xor circuit
Which most popular input device is used today for interactive processing and for the one line entry of data for batch processing?
1.Mouse
2.Magnetic disk
3.Visual display terminal
4. Card punch
DDR stands for __________
1.Data Direction Register
2.Data Decoding Register
3. Data Decoding Rate
4.None of the mentioned
IDE stands for _________
1.Integrated Device Electronics
2.International Device Encoding
3.Industrial Decoder Electronics
4.International Decoder Encoder
In a general 8-bit parallel interface, the INTR line is connected to _______
1.Status and Control unit
2. DDR
3.Register select
4. None of the mentioned
In a serial port interface, the INTR line is connected to _____
1. Status register
2.Shift register
3. Chip select
4.None of the mentioned
IRDY# signal is used for _______
1. Selecting the interrupt line
2.Sending an interrupt
3.Saying that the initiator is ready
4.None of the mentioned
ISO stands for __________
1.International Standards Organisation
2.International Software Organisation
3.Industrial Standards Organisation
4. Industrial Software Organisation
The Interface circuits generate the appropriate timing signals required by the BUS control scheme.
1.TRUE
2. False
PCI stands for _______
1.Peripheral Component Interconnect
2.Peripheral Computer Internet
3.Processor Computer Interconnect
4. Processor Cable Interconnect
SCSI stands for ___________
1.Signal Computer System Interface
2. Small Computer System Interface
3.Small Coding System Interface
4. Signal Coding System Interface
The best mode of connection between devices which need to send or receive large amounts of data over a short distance is _____
1.BUS
2.Serial port
3. Parallel port
4. Isochronous port
The data transfer in UART is done in ______
1. Asynchronous start stop format
2.Synchronous start stop format
3.Isochronous format
4.EBDIC format
The device connected to the BUS are given addresses of ____ bit.
1.24
2.64
3.32
4.16
The double buffer is used for _________
1.Enabling retrieval of multiple bits of input
2.Combining the input and output operations
3.Extending the buffer capacity
4.None of the mentioned
The key feature of UART is _________
1. Its architectural design
2.Its simple implementation
3.ts general purpose usage
4. Its enhancement of connecting low speed devices
The master is also called as _____ in PCI terminology.
1.Initiator
2.Commander
3. Chief
4.Starter
The mode of transmission of data, where one bit is sent for each clock cycle is ______
1.Asynchronous
2.Parallel
3.Serial
4.Isochronous
The output of the encoder circuit is/are ______
1.ASCII code
2.ASCII code and the valid signal
3.Encoded signal
4.None of the mentioned
The PCI BUS has _____ interrupt request lines.
1.6
2.1
3.4
4.3
The PCI BUS supports _____ address space/s.
1. I/O
2.Memory
3.Configuration
4.All of the mentioned
The PCI follows a set of standards primarily used in _____ PC’s.
1.Intel
2.Motorola
3. IBM
4. SUN
The serial port is used to connect basically _____ and processor.
1.I/O devices
2.Speakers
3.Printer
4.Monitor
The standard used in serial ports to facilitate communication is _____
1.RS-246
2.RS-LNK
3.RS-232-C
4.Both RS-246 and RS-LNK
The status flags required for data transfer is present in _____
1.Device
2.Device driver
3.Interface circuit
4.None of the mentioned
The system developed by IBM with ISA architecture is ______
1.SPARC
2.SUN-SPARC
3.PC-AT
4. None of the mentioned
The transformation between the Parallel and serial ports is done with the help of ______
1. Flip flops
2.Logic circuits
3.Shift registers
4.None of the mentioned
The transformation between the Parallel and serial ports is done with the help of ______
1.Flip flops
2.Logic circuits
3.Shift registers
4.None of the mentioned
The use of spooler programs or _______ Hardware allows PC operators to do the processing work at the same time a printing operation is in progress.
1.Registers
2.Memory
3.Buffer
4. CPU
The video devices are connected to ______ BUS.
1. PCI
2.USB
3.HDMI
4.SCSI
The _____ circuit enables the generation of the ASCII code when the key is pressed.
1. Generator
2.Debouncing
3.Encoder
4. Logger
The ______ is the BUS used in Macintosh PC’s.
1.NuBUS
2. EISA
3.PCI
4.None of the mentioned
To overcome multiple signals being generated upon a single press of the button, we make use of ______
1.Generator circuit
2. Debouncing circuit
3.Multiplexer
4. XOR circuit
UART stands for ________
1. Universal Asynchronous Relay Transmission
2.Universal Accumulator Register Transfer
3.Universal Asynchronous Receiver Transmitter
4.None of the mentioned
UART stands for ________
1.Universal Asynchronous Relay Transmission
2.Universal Accumulator Register Transfer
3.Universal Asynchronous Receiver Transmitter
4.None of the mentioned
User programmable terminals that combine VDT hardware with built-in microprocessor is _____
1. KIPs
2.Pc
3. Mainframe
4.Intelligent terminals
What is the full form of ANSI?
1.American National Standards Institute
2.Architectural National Standards Institute
3.Asian National Standards Institute
4.None of the mentioned
What is the full form of ISA?
1.International American Standard
2.Industry Standard Architecture
3. International Standard Architecture
4. None of the mentioned
When transferring data over the PCI BUS, the master as to hold the address until the completion of the transfer to the slave.
1.TRUE
2.FALSE
____ address space gives the PCI its plug and plays capability.
1.Configuration
2. I/O
3.Memory
4.All of the mentioned
____ provides a separate physical connection to the memory.
1.PCI BUS
2.PCI interface
3. PCI bridge
4. PCI bridge
____ signal is sent by the initiator to indicate the duration of the transaction.
1.FRAME#
2.IRDY#
3.TMY#
4.SELD#
_____ is used as an intermediate to extend the processor BUS.
1. Bridge
2.Router
3.Connector
4.Gateway
_____ to increase the flexibility of the serial ports.
1.The wires used for ports is changed
2.The ports are made to allow different clock signals for input and output
3.The drivers are modified
4.All of the mentioned
_____ to increase the flexibility of the serial ports.
1. The wires used for ports is changed
2.The ports are made to allow different clock signals for input and output
3.The drivers are modified
4.All of the mentioned
_______ is an extension of the processor BUS.
1. SCSI BUS
2.USB
3. PCI BUS
4.None of the mentioned