Computer/MCQ Computer Organisation - Input Sample Test,Sample questions

Question:
 In synchronous BUS, the devices get the timing signals from __________

1.Timing generator in the device

2.A common clock line

3.Timing signals are not used at all

4. None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
After the device completes its operation _____ assumes the control of the BUS.

1. Another device

2. Processor

3.Controller

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
Asynchronous mode of transmission is suitable for systems with multiple peripheral devices.

1.TRUE

2. False

Posted Date:-2021-03-14 23:09:27


Question:
 If two devices A and B contesting for the BUS have ID’s 5 and 6 respectively, which device gets the BUS based on the Distributed arbitration.

1.Device A

2.Device B

3.Insufficient information

4. None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
 In IBM’s S360/370 systems _____ lines are used to select the I/O devices.

1.SCAN in and out

2. Connect

3.Search

4.Peripheral

Posted Date:-2021-03-14 23:09:27


Question:
 The asynchronous BUS mode of transmission allows for a faster mode of data transfer.

1.TRUE

2.FALSE

Posted Date:-2021-03-14 23:09:27


Question:
 The conversion from parallel to serial data transmission and vice versa takes place inside the interface circuits.

1.TRUE

2. False

Posted Date:-2021-03-14 23:09:27


Question:
 The device which is allowed to initiate data transfers on the BUS at any time is called _____

1.BUS master

2.Processor

3.BUS arbitrator

4.Controller

Posted Date:-2021-03-14 23:09:27


Question:
 The DMA transfer is initiated by _____

1.Processor

2.The process being executed

3. I/O devices

4.OS

Posted Date:-2021-03-14 23:09:27


Question:
 The registers of the controller are ______

1.64 bits

2. 24 bits

3. 32 bits

4.16 bits

Posted Date:-2021-03-14 23:09:27


Question:
 The side of the interface circuits, that has the data path and the control signals to transfer data between interface and device is _____

1.BUS side

2.Port side

3. Hardwell side

4.Software side

Posted Date:-2021-03-14 23:09:27


Question:
 When the R/W bit of the status register of the DMA controller is set to 1.

1.Read operation is performed

2.Write operation is performed

3.Read & Write operation is performed

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
Can a single DMA controller perform operations on two different disks simultaneously?

1.TRUE

2.FALSE

Posted Date:-2021-03-14 23:09:27


Question:
Distributed arbitration makes use of ______

1.BUS master

2.Processor

3.Arbitrator

4.4-bit ID

Posted Date:-2021-03-14 23:09:27


Question:
How is a device selected in Distributed arbitration?

1.By NANDing the signals passed on all the 4 lines

2.By ANDing the signals passed on all the 4 lines

3. By ORing the signals passed on all the 4 lines

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
In Centralised Arbitration ______ is/are is the BUS master.

1.Processor

2.DMA controller

3. Device

4.Both Processor and DMA controller

Posted Date:-2021-03-14 23:09:27


Question:
In Distributed arbitration, the device requesting the BUS ______

1.Asserts the Start arbitration signal

2.Sends an interrupt signal

3.Sends an acknowledge signal

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
 The DMA controller has _______ registers.

1.4

2.2

3.3

4.1

Posted Date:-2021-03-14 23:09:27


Question:
MRDC stands for _______

1.Memory Read Enable

2.Memory Ready Command

3.Memory Re-direct Command

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
Once the BUS is granted to a device ___________

1. It activates the BUS busy line

2. Performs the required operation

3.Raises an interrupt

4.All of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
The BUS busy line is made of ________

1. Open-drain circuit

2.Open-collector circuit

3.EX-Or circuit

4.Nor circuit

Posted Date:-2021-03-14 23:09:27


Question:
The BUS busy line is used __________

1.To indicate the processor is busy

2. To indicate that the BUS master is busy

3.To indicate the BUS is already allocated

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
The BUS that allows I/O, memory and Processor to coexist is _______

1.Attributed BUS

2. Processor BUS

3.Backplane BUS

4.External BUS

Posted Date:-2021-03-14 23:09:27


Question:
The Centralised BUS arbitration is similar to ______ interrupt circuit.

1.Priority

2.Parallel

3.Single

4.Daisy chain

Posted Date:-2021-03-14 23:09:27


Question:
The circuit used for the request line is a _________

1.Open-collector

2.EX-OR circuit

3.Open-drain

4.Nand circuit

Posted Date:-2021-03-14 23:09:27


Question:
The classification of BUSes into synchronous and asynchronous is based on _______

1.The devices connected to them

2.The type of data transfer

3.The Timing of data transfers

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
The controller is connected to the ____

1.Processor BUS

2.System BUS

3.External BUS

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
The controller uses _____ to help with the transfers when handling network interfaces.

1. Input Buffer storage

2.Signal enhancers

3.Bridge circuits

4.All of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
The delays caused in the switching of the timing signals is due to __________

1. Memory access time

2.WMFC

3.Propagation delay

4. Processor delay

Posted Date:-2021-03-14 23:09:27


Question:
The device which interacts with the initiator is __________

1. Slave

2.Master

3.Responder

4. Friend

Posted Date:-2021-03-14 23:09:27


Question:
The device which starts data transfer is called __________

1. Master

2.Transactor

3.Distributor

4.Initiator

Posted Date:-2021-03-14 23:09:27


Question:
The devices with variable speeds are usually connected using asynchronous BUS.

1.TRUE

2.FALSE

Posted Date:-2021-03-14 23:09:27


Question:
The master indicates that the address is loaded onto the BUS, by activating _____ signal.

1.MSYN

2.SSYN

3.WMFC

4.INTR

Posted Date:-2021-03-14 23:09:27


Question:
The Master strobes the slave at the end of each clock cycle in Synchronous BUS

1.TRUE

2.FALSE

Posted Date:-2021-03-14 23:09:27


Question:
The meter in and out lines are used for __________

1.Monitoring the usage of devices

2.Monitoring the amount of data transferred

3.Measure the CPU usage

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
The MSYN signal is initiated __________

1.Soon after the address and commands are loaded

2.Soon after the decoding of the address

3.After the slave gets the commands

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
The parallel mode of communication is not suitable for long devices because of ______

1.Timing skew

2. Memory access delay

3.Latency

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
The primary function of the BUS is __________

1.To connect the various devices to the cpu

2.To provide a path for communication between the processor and other devices

3.To facilitate data transfer between various devices

4.All of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
The technique where the controller is given complete access to main memory is __________

1.Cycle stealing

2.Memory stealing

3. Memory Con

4. Burst mode

Posted Date:-2021-03-14 23:09:27


Question:
The technique whereby the DMA controller steals the access cycles of the processor to operate is called _________

1. Fast conning

2.Memory Con

3.Cycle stealing

4.Memory stealing

Posted Date:-2021-03-14 23:09:27


Question:
The time for which the data is to be on the BUS is affected by __________

1.Propagation delay of the circuit

2. Setup time of the device

3.Memory access time

4.Propagation delay of the circuit & Setup time of the device

Posted Date:-2021-03-14 23:09:27


Question:
The transmission on the asynchronous BUS is also called _____

1.Switch mode transmission

2. Variable transfer

3.Bulk transfer

4.Hand-Shake transmission

Posted Date:-2021-03-14 23:09:27


Question:
To overcome the conflict over the possession of the BUS we use ______

1.Optimizers

2. BUS arbitrators

3. Multiple BUS structure

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
To resolve the clash over the access of the system BUS we use ______

1.Multiple BUS

2.BUS arbitrator

3.Priority access

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
What is the interface circuit?

1.Helps in installing of the software driver for the device

2. Houses the buffer that helps in data transfer

3. Helps in the decoding of the address on the address BUs

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
When the process requests for a DMA transfer?

1.Then the process is temporarily suspended

2.The process continues execution

3.Another process gets executed

4.process is temporarily suspended & Another process gets executed

Posted Date:-2021-03-14 23:09:27


Question:
When the processor receives the request from a device, it responds by sending _____

1.Acknowledge signal

2. BUS grant signal

3.Response signal

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
Which is fed into the BUS first by the initiator?

1.Data

2.Address

3.Commands or controls

4.Address, Commands or controls

Posted Date:-2021-03-14 23:09:27


Question:
___ BUS arbitration approach uses the involvement of the processor.

1.Centralised arbitration

2.Distributed arbitration

3.Random arbitration

4.All of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
_____ serves as an intermediary between the device and the BUSes.

1.Interface circuits

2.Device drivers

3.Buffers

4.None of the mentioned

Posted Date:-2021-03-14 23:09:27


Question:
____________ signal is used as an acknowledgement signal by the slave in Multiple cycle transfers.

1.Ack signal

2.Slave ready signal

3. Master ready signal

4.Slave received signal

Posted Date:-2021-03-14 23:09:27


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